Today, there is great emphasis on increasing the speed of computer systems. Typically, the speed of computer systems is dictated by the speed at which the processor within the computer system can operate. Therefore, the speed of a computer system can be increased by the use of a faster processor (or associated co-processor where the case may be). One prior art technique for increasing the speed of a processor, and thus increase the speed of a computer system, is to use pipelining. In pipelining, the execution of individual instructions is overlapped. By overlapping instruction execution, the computer system achieves parallelism.
When implementing pipelining, the execution of an individual instruction is broken down into stages. As each instruction completes one particular stage and moves to the next, the following instruction begins executing at that stage, such that the overall throughput of a computer system (i.e., how often an instruction completes execution in the pipeline) is approximately one cycle time.
Another technique utilized in microprocessors to achieve more parallelism in the execution process is to employ multiple execution units. For instance, in the case of superscalar processors, multiple integer and floating point execution units are utilized for executing multiple instructions at the same time. In other words, while one instruction is being executed in one of the execution units, another instruction may be executed in another execution unit. In this manner, multiple instructions are executed at one time. The use of multiple execution units often are utilized in multiple pipeline systems in which a separate pipeline, or portion thereof, is employed in configuration with a distinct execution unit. In this case, multiple instructions can be executed in multiple execution pipelines to increase the throughput. Therefore, it is desirable to have a processor which is capable of executing multiple instructions at the same time, thereby increasing the speed at which a processor can execute a program.
Normally, in any particular program executed by a processor, a portion of the instructions control the flow of the program itself. These are typically referred to as control flow instructions. Examples of control flow instructions are branch instructions and loop maintenance instructions. Branch instructions cause a program to jump to another portion of a program or program memory. The address to which the branch instruction jumps may be an absolute address or an address relative to the current location in program memory. Some branch instructions are conditional such that the branch occurs only upon the occurrence of a predetermined condition or the setting of a flag in a predetermined manner. Loop maintenance instructions are those instructions which maintain the loop counters and the loop states. In today's processors, general purpose registers are used to maintain loop counters and loop states.
In prior art programming models, these control flow instructions are usually dependent on the data manipulations being performed by the computer system. Furthermore, the main execution cycles of the main arithmetic pipeline(s) are required to modify loop counters and states and to perform branches. Because the main arithmetic pipeline(s) are required to execute these control flow instructions, the time at which the main pipeline can perform data computations is reduced, thereby decreasing the throughput of data computations. It is desirable to relieve this main arithmetic pipelines from having to perform loop maintenance operations and control flow instructions, such that the main arithmetic pipelines can be used solely for data computations, thereby making the computation faster.
Another type of control instruction is a CASE instruction. A CASE instruction is a modified branch instruction which, upon execution, allows the program to jump to more than one location according to a predetermined number of conditions. In other words, upon executing a CASE instruction, if a first set of conditions is met, the program jumps to a first location; however, if a second set of conditions exists, the program instead jumps to a second location in the program memory instead, etc. CASE instructions are capable of supporting numerous conditional branches (e.g., 3, 4, 5, etc.).
In the prior art, when a CASE instruction is utilized in a program, all of the addresses (i.e., memory locations) corresponding to all of the possible branch locations are encoded into the instruction itself. For example, a CASE instruction supporting four possible branches to different memory locations would have four separate addresses (or address displacements) encoded into the instruction. The result of having memory addresses encoded into the instruction stream is a large instruction, which requires increased effort in decoding and execution and requires more space in a program memory. Because memory space is at a premium, it is desirable to use short instructions that require less space in program memory. It is also desirable to be able to invoke the function of a CASE instruction using an instruction of standard length. Moreover, when a CASE instruction is being executed, each condition must be evaluated in sequence to determine if the conditions are satisfied. The greater the number of conditions, the longer the time necessary to check all of the possible branching conditions to them required by the CASE instructions. Therefore, the execution of a CASE instruction requires multiple cycles to complete. It is desirable to be able to perform a CASE instruction in one cycle.
As will be shown, the present invention provides a separate control pipeline for executing control flow instructions and performing loop maintenance, such that the main arithmetic pipelines may be used solely for data computations.